Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications

A message oriented interprocessor communication network is proposed that utilizes a simple fixed algorithm to store-and-forward short messages over directed data lines. The modular design of the network permits message transmission along a variable number of processors. Simulations of the network´s performance indicate that for appropriate message loads the network transmits messages in time proportional to the square root of the number of processors served.