A technique for dynamic CMOS noise immunity evaluation

While dynamic CMOS logic is considered an attractive circuit technique, it suffers from noise problems. Noise may affect dynamic CMOS circuits in many ways. In this paper, new models have been developed that consider a noise pulse on one of the circuit inputs or on the clock input. These models specify the circuit noise immunity in terms of both the amplitude and the duration of a noise pulse. HSPICE simulations confirm the validity of these models for both long and short-channel MOSFETs. As dynamic circuits are designed around the constraint of noise, the models presented here clearly indicate parameters that affect noise and their influence, and how it could aid digital circuit designs.