DocumentCode :
1148289
Title :
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer
Author :
Tsang, Kevin ; Wei, Belle W Y
Author_Institution :
Dept. of Electr. Eng., San Jose State Univ., CA, USA
Volume :
2
Issue :
3
fYear :
1994
Firstpage :
360
Lastpage :
364
Abstract :
Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator and encoder of 512/spl times/512 images at 30 frames/s. The four-chip 0.8 /spl mu/m CMOS design implements a tree of Kohonen self-organizing maps, and consists of two VQ processors and two image buffer memory chips. The pipelined VQ processor contains a computational core for both code book generation and encoding, and is scalable to processing larger frames.<>
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; image coding; image processing equipment; neural chips; parallel architectures; pipeline processing; real-time systems; self-organising feature maps; vector quantisation; 0.8 micron; 262144 pixel; 512 pixel; CMOS design; Kohonen self-organizing maps; VLSI architecture; dynamic code book generation; image buffer memory chips; image compression; pipelined VQ processor; real-time code book generator; real-time encoder; vector quantization; Books; Computer architecture; Decoding; Hardware; Image coding; Image quality; Neurons; PSNR; Vector quantization; Very large scale integration;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.311645
Filename :
311645
Link To Document :
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