DocumentCode :
1149446
Title :
An improved scaled DCT architecture
Author :
Wu, Zhigang ; Sha, Jin ; Wang, Zhongfeng ; Li, Li ; Gao, Minglun
Author_Institution :
Dept. of Phys., Nanjing Univ., Nanjing, China
Volume :
55
Issue :
2
fYear :
2009
fDate :
5/1/2009 12:00:00 AM
Firstpage :
685
Lastpage :
689
Abstract :
This paper presents an efficient architecture for computing the eight-point 1D scaled DCT (discrete cosine transform) with a new algorithm based on a selected Loeffler DCT scheme whose multiplications are placed in the last stage. The proposed DCT architecture does not require any scaling compensation in the computation. Furthermore, a multiplication approximation method is developed, which is more efficient than traditional CORDIC (coordinate rotation digital computer)-based algorithms. Compared to the latest work (Sun et al., 2007), the proposed approach can save 14% addition operations for the same precision requirement and the path delay can be significantly reduced as well.
Keywords :
digital arithmetic; discrete cosine transforms; multiplying circuits; CORDIC algorithm; Loeffler DCT; coordinate rotation digital computer-based algorithm; discrete cosine transform; eight-point 1D scaled DCT architecture; multiplication approximation; path delay; Approximation algorithms; Approximation methods; Computer architecture; Delay; Discrete cosine transforms; Hardware; Iterative algorithms; Karhunen-Loeve transforms; Quantization; Robustness; DCT, Scaled DCT, CORDIC algorithm.;
fLanguage :
English
Journal_Title :
Consumer Electronics, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-3063
Type :
jour
DOI :
10.1109/TCE.2009.5174440
Filename :
5174440
Link To Document :
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