DocumentCode :
1151496
Title :
CPAC—Concurrent Processor Architecture for Control
Author :
Jaswa, Vijay C. ; Thomas, Charles E. ; Pedicone, John T.
Author_Institution :
System Industries
Issue :
2
fYear :
1985
Firstpage :
163
Lastpage :
169
Abstract :
We describe a computer architecture for implementing real-time controllers. The concurrent processor architecture for control (CPAC) is optimized for computing the state transitions of a controller. While general-purpose computers are optimized for data manipulation, CPAC is optimized for state manipulation since the states of a controller and the rules governing state transitions constitute a complete high-level description of a controller implementation. The CPAC architecture characterizes a controller in terms of the sets of continuous and discrete states of the system and-logically as well as physically separates the two sets. This dichotomy results in a simpler specification of the rules for state transitions.
Keywords :
Computer architecture; VLSI; concurrent processing; controls; programmable control; real-time; real-time control; Computer architecture; Concurrent computing; Control systems; Electric variables control; Equations; Microprocessors; Pi control; Process control; Proportional control; Signal processing algorithms; Computer architecture; VLSI; concurrent processing; controls; programmable control; real-time; real-time control;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.1985.1676553
Filename :
1676553
Link To Document :
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