Title :
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling
Author :
Tan, Sheldon X -D ; Shi, C. J Richard
Author_Institution :
Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA
fDate :
3/1/2003 12:00:00 AM
Abstract :
We present an efficient method of minimizing the area of power/ground (P/G) networks in integrated circuit layouts subject to reliability constraints. Instead of directly sizing the original P/G network extracted from a circuit layout, as done previously, the new method first constructs a reduced but electrically equivalent P/G network. Then the sequence of linear programming method is applied to optimize the reduced network. The solution of the original network is then backsolved from the optimized reduced network. The new method exploits the regularities in the P/G networks to reduce the complexities of P/G networks. Experimental results show that the sizes of reduced networks are typically significantly smaller than that of the original networks. The resulting algorithm is fast enough that P/G networks with more than one million branches can be sized in a few minutes on modern Sun workstations.
Keywords :
VLSI; circuit optimisation; equivalent circuits; integrated circuit layout; integrated circuit modelling; integrated circuit reliability; linear programming; VLSI; area minimization; circuit optimization; circuit reliability; equivalent circuit model; integrated circuit layout; power distribution; power/ground network sizing algorithm; sequence of linear programming method; Capacitance; Electromigration; Equivalent circuits; Integrated circuit layout; Integrated circuit reliability; Linear programming; Network topology; Optimization methods; Very large scale integration; Wire;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2002.807883