Title :
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
Author :
Liu, Yu-cheng ; Jou, Chi-jiunn
Author_Institution :
Department of Electrical Engineering, The University of Texas
fDate :
6/1/1987 12:00:00 AM
Abstract :
This correspondence presents two expressions in calculating effective memory bandwidth for a wide range of multiple-bus configurations. Also presented is an analytical solution for determining each processor´s blocking probability in a multiple-bus system where different priorities are assigned to the processors.
Keywords :
Crossbar; effective memory bandwidth; multiple-bus; partially connected multiple-bus; processor blocking probability; Bandwidth; Costs; Degradation; Equations; Multiprocessing systems; Performance analysis; Power system modeling; Probability; System buses; System performance; Crossbar; effective memory bandwidth; multiple-bus; partially connected multiple-bus; processor blocking probability;
Journal_Title :
Computers, IEEE Transactions on
DOI :
10.1109/TC.1987.1676968
