Parallel architectures for 3-step hierarchical search block-matching algorithm

Author

Jong, Her-Ming ; Liang-Gee ; Chiueh, Tzi-Dar

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

4

Issue

4

fYear

1994

fDate

8/1/1994 12:00:00 AM

Firstpage

407

Lastpage

416

Abstract

The paper describes fully pipelined parallel architectures for the 3-step hierarchical search block-matching algorithm, a fast motion estimation algorithm for video coding. The advantage of this algorithm was completely utilized by use of intelligent data arrangement and memory configuration. Techniques for reducing interconnections and external memory accesses were also developed. Because of their low costs, high speeds, and low memory bandwidth requirements, the proposed 3-PE, 9-PE, and 27-PE architectures provide efficient solutions for real-time motion estimations required by video applications of various data rates, from low bit-rate video to HDTV systems

Keywords

buffer storage; data compression; digital signal processing chips; high definition television; image coding; image sequences; memory architecture; motion estimation; parallel architectures; parameter estimation; pipeline processing; random-access storage; search problems; video signals; 27-PE architecture; 3-PE architecture; 3-step hierarchical search block-matching algorithm; 9-PE architecture; HDTV; data rates; external memory accesses; fast motion estimation algorithm; fully pipelined parallel architectures; intelligent data arrangement; interconnections; low bit-rate video; memory configuration; real-time motion estimations; video applications; video coding; Bandwidth; Computational complexity; Computer architecture; Costs; HDTV; Motion estimation; Parallel architectures; Real time systems; Video coding; Video compression;

fLanguage

English

Journal_Title

Circuits and Systems for Video Technology, IEEE Transactions on

Publisher

ieee

ISSN

1051-8215

Type

jour

DOI

10.1109/76.313135

Filename

313135