DocumentCode :
1160184
Title :
High-Density Reduced-Stack Logic Circuit Techniques Using Independent-Gate Controlled Double-Gate Devices
Author :
Chiang, Meng-Hsueh ; Kim, Keunwoo ; Chuang, Ching-Te ; Tretz, Christophe
Author_Institution :
Dept. of Electron. Eng., Nat. Ilan Univ.
Volume :
53
Issue :
9
fYear :
2006
Firstpage :
2370
Lastpage :
2377
Abstract :
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations
Keywords :
CMOS logic circuits; logic gates; numerical analysis; CMOS logic; DG devices; DG technology; controlled double-gate devices; high-density logic circuit; independent-gate devices; logic gate; mixed-mode numerical simulations; physics-based numerical simulations; polysilicon gate; reduced-stack logic circuit; series-connected stack portion; threshold voltage; CMOS logic circuits; CMOS technology; Capacitance; Circuit optimization; Logic circuits; Logic devices; Logic functions; Logic gates; MOSFETs; Numerical simulation; CMOS logic; double-gate (DG) devices; threshold voltage (;
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2006.881052
Filename :
1677877
Link To Document :
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