DocumentCode :
1161226
Title :
Logic design verification via test generation
Author :
Abadir, Magdy S. ; Ferguson, Jack ; Kirkland, Thomas E.
Author_Institution :
Microelectron. & Comput. Technol. Corp., Austin, TX, USA
Volume :
7
Issue :
1
fYear :
1988
fDate :
1/1/1988 12:00:00 AM
Firstpage :
138
Lastpage :
148
Abstract :
A method for logic design verification is introduced in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns that were developed to detect single stuck-line faults in the gate-level implementation are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large
Keywords :
logic design; logic testing; design errors; gate-level implementation; logic design verification; test generation; test patterns; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Inverters; Logic design; Logic testing; Microelectronics; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.3141
Filename :
3141
Link To Document :
بازگشت