Internal thermal resistance of a multi-chip packaging design for VLSI based systems

A heat-transfer study is conducted for the steady-state internal thermal resistance of a multichip packaging technology for VLSI-based systems. This technology, which is known as advanced VLSI packaging (AVP), has chips flip-chip soldered and interconnected on a silicon substrate. AVP´s thermal management approach is to dissipate chip power through the silicon substrate to a heat sink or other packaging levels. The authors found a need to control the chip-to-substrate interface; therefore, they use a three-dimensional heat conduction analysis to characterize this interface. They simulate thermal performance of typical AVP assemblies affected by thermal vias, solder bump heights, high-power I O drivers, and chip sizes. The authors also analyze and measure the internal resistances of an experimental package consisting of three WE32100 chips. These resistances are predicted as 3.7, 4.7, and 5.0°C/W, respectively; they are confirmed by the experimental data. The authors demonstrate the low thermal resistance achieved: 3.0°C/W for a 1-cm square chip and 10°C/W for a 0.25-cm square chip. They also provide their insight into the roles of different conduction paths involved