• DocumentCode
    1162288
  • Title

    Shunting neural network photodetector arrays in analog CMOS

  • Author

    Nilson, Christopher Donald ; Darling, Robert B. ; Pinter, Robert B.

  • Author_Institution
    Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
  • Volume
    29
  • Issue
    10
  • fYear
    1994
  • fDate
    10/1/1994 12:00:00 AM
  • Firstpage
    1291
  • Lastpage
    1296
  • Abstract
    This paper describes a custom analog CMOS photodetector array IC that exploits nonlinear lateral inhibition to achieve dynamic range compression, edge enhancement, and adaptation to mean input intensity. The neural net array architecture, characterized by nearest-neighbor connections and multiplicative cell interaction, is modeled after biological vision systems. The fabricated IC successfully implements a portion of the compact and powerful nonlinear signal processing performed in the outer layers of the vertebrate retina. Measured results are presented for an optical input intensity range of nearly six decades. A scanning architecture that allows for preferential directional sensitivity is also demonstrated. Measured data agree well with models created using a spreadsheet program
  • Keywords
    CMOS integrated circuits; analogue processing circuits; application specific integrated circuits; image processing equipment; image sensors; linear integrated circuits; neural chips; photodetectors; custom analog CMOS photodetector array IC; dynamic range compression; edge enhancement; multiplicative cell interaction; nearest-neighbor connections; neural net array architecture; nonlinear lateral inhibition; nonlinear signal processing; preferential directional sensitivity; scanning architecture; shunting neural network photodetector arrays; Adaptive arrays; Analog integrated circuits; Biological system modeling; CMOS analog integrated circuits; CMOS integrated circuits; Cells (biology); Dynamic range; Neural networks; Optical signal processing; Photodetectors;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.315217
  • Filename
    315217