A single-chip 16-bit 25-ns real-time video/image signal processor

Author

Kikuchi, Kouichi ; Nukada, Yasuaki ; Aoki, Yasushi ; Kanou, Toshiyuki ; Endo, Yukio ; Nishitani, Takao

Author_Institution

NEC Corp., Kawasaki, Japan

Volume

24

Issue

6

fYear

1989

fDate

12/1/1989 12:00:00 AM

Firstpage

1662

Lastpage

1667

Abstract

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors

Keywords

CMOS integrated circuits; VLSI; computerised picture processing; digital signal processing chips; encoding; pipeline processing; real-time systems; telecommunications computing; teleconferencing; television equipment; video equipment; video signals; visual communication; 16 bit; 25 ns; TV conference systems; VLSI; complementary reduced-swing CMOS logic circuits; double-metal-layer; image signal processor; instruction cycle time; low-bit-rate transmission; microprocessor functional units; microprogrammable DSP; multiple-chip connections; real-time motion picture encoding; seven-stage pipeline arithmetic circuit; video signal processor; Arithmetic; Circuits; Image coding; Microprocessors; Motion pictures; Pipelines; Real time systems; Signal processing; TV; Videoconference;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.45003

Filename

45003