DocumentCode :
1162819
Title :
Gate matrix partitioning
Author :
Huang, Shuo ; Wing, Omar
Author_Institution :
Columbia Univ., New York, NY, USA
Volume :
8
Issue :
7
fYear :
1989
fDate :
7/1/1989 12:00:00 AM
Firstpage :
756
Lastpage :
767
Abstract :
An algorithm is presented which partitions a gate matrix into a number of matrices such that the total area and the aspect ratio of the circumscribing rectangle are improved. The algorithm is based on the min-cut algorithm. The gain function and the balance condition are redefined for the gate matrix problem. The time complexity of the algorithm is O(t)+O(|NI|2), where t is the number of gate-net intersections, and NI the subset of nets that intersect long gates. A novel gate-sequencing algorithm, designed for assigning gates in the partitioned gate matrices simultaneously, is introduced. By using the simultaneous-gate-sequencing algorithm, the partitioned gate matrices are connected by sharing gates. Since the same column is used for a gate shared by adjacent matrices, the layout does not require extra routing area. Experimental results show significant improvement over the layout without partition. For the three examples used in a previous paper, the area reduction ranges from 11-41%. The aspect ratio improves from 2.63, 4.00, and 2.59 to 1.04, 1.22, and 1.28, respectively
Keywords :
CMOS integrated circuits; circuit layout CAD; matrix algebra; CMOS layout style; area reduction; aspect ratio; balance condition; circumscribing rectangle; gain function; gate matrix partitioning; gate-net intersections; gate-sequencing algorithm; layout; min-cut algorithm; routing area; time complexity; Algorithm design and analysis; Helium; Partitioning algorithms; Routing;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.31533
Filename :
31533
Link To Document :
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