• DocumentCode
    1162825
  • Title

    A VLSI design for a trace-back Viterbi decoder

  • Author

    Truong, T.K. ; Shih, Ming-Tang ; Reed, Irving S. ; Satorius, E.H.

  • Author_Institution
    Commun. Syst. Res. Section, Jet Propulsion Lab., Pasadena, CA, USA
  • Volume
    40
  • Issue
    3
  • fYear
    1992
  • fDate
    3/1/1992 12:00:00 AM
  • Firstpage
    616
  • Lastpage
    624
  • Abstract
    A systolic Viterbi decoder for convolutional codes is developed which uses the trace-back method to reduce the amount of data needed to be stored in registers. It is shown that this new algorithm requires a smaller chip size and achieves a faster decoding time than other existing methods
  • Keywords
    VLSI; decoding; error correction codes; systolic arrays; VLSI design; convolutional codes; decoding time; registers; systolic Viterbi decoder; trace-back Viterbi decoder; Convolutional codes; Decoding; Forward error correction; Hardware; Laboratories; Propulsion; Shift registers; Signal processing algorithms; Very large scale integration; Viterbi algorithm;
  • fLanguage
    English
  • Journal_Title
    Communications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0090-6778
  • Type

    jour

  • DOI
    10.1109/26.135732
  • Filename
    135732
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1162825