Interconnection delay in very high-speed VLSI

Interconnection delay of VLSI in high-speed digital systems is addressed. A formal analysis of the signal propagation delay in VLSI circuits is presented. It is shown that, depending on the circuit parameters, there are basically two delay domains: the RC delay domain and the transmission-line-delay domain. The results derived from the more traditional lumped-RC model mainly capture the properties of the RC delay domain. However, in the transmission-line-delay domain the wire inductance becomes an important factor, and hence RC modeling is no longer adequate to estimate the delay. Two delay formulas are derived in this paper for the RC delay domain and the transmission-line-delay domain. The effect of feature size scaling on VLSI circuit performance is evaluated, and the inherent limitation on scaling due to interconnection delay is discussed. Finally, the relationship between delay and technology parameters such as wire resistance, capacitance, inductance, wire width and length, and load capacitance is investigated to provide design guidelines