DocumentCode :
1162971
Title :
Systolic array implementation of multipliers for finite fields GF(2m)
Author :
Wang, Chin-Liang ; Lin, Jung-lung
Author_Institution :
Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
38
Issue :
7
fYear :
1991
fDate :
7/1/1991 12:00:00 AM
Firstpage :
796
Lastpage :
800
Abstract :
A parallel-in-parallel-out systolic array and a serial-in-serial-out systolic array are proposed for fast multiplication in finite fields GF(2m) with the standard basis representation. Both of the architectures possess features of regularity, modularity, concurrency, and unidirectional data flow. As a consequence, they have high throughput rates and are well suited to VLSI implementation with fault-tolerant design. As compared to the related multipliers presented by C.S. Yeh et al. (see IEEE Trans. Comput., vol.C-33, p.357-360, Apr. 1984), the proposed parallel implementation makes it easier to incorporate fault-tolerant design, and the proposed serial implementation requires only one control signal instead of two
Keywords :
VLSI; multiplying circuits; parallel architectures; systolic arrays; concurrency; control signal; fault-tolerant design; finite fields; modularity; multipliers; parallel-in-parallel-out systolic array; regularity; serial-in-serial-out systolic array; standard basis representation; throughput rates; unidirectional data flow; Algorithm design and analysis; Circuits; Design optimization; Digital filters; Finite impulse response filter; Galois fields; IIR filters; Signal processing algorithms; Speech processing; Systolic arrays;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/31.135751
Filename :
135751
Link To Document :
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