Title :
A parity bit signature for exhaustive testing
Author :
Akers, Sheldon B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fDate :
3/1/1988 12:00:00 AM
Abstract :
A parity bit signature particularly well suited for exhaustive testing techniques is defined and discussed. The discussion is concerned not only with the proposed parity bit signature itself, but also with the general problem of evaluating its effectiveness relative to a given implementation. In addition to such desirable properties as uniformity and ease of implementation, it is shown to be especially amenable to efficient fault coverage calculations
Keywords :
automatic testing; logic testing; combinational circuits; exhaustive testing techniques; fault coverage calculations; logic testing; parity bit signature; Analytical models; Automatic testing; Built-in self-test; Cause effect analysis; Circuit faults; Circuit testing; Compaction; Pattern analysis; Proposals; Test pattern generators;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
