High-Speed Power Flows Using Attached Scientific ("Array") Processors

The array processor is a comparatively recent innovation in computer architecture which promises large amounts of inexpensive computing power on fairly large problems. In particular, it is able to handle problems involving large, sparse matrix manipulations without serious degradation in performance. One such problem is the AC Power Flow simulation. This paper describes the implementation of Stott\´s Fast Decoupled Power Flow algorithm on the Floating Point Systems AP-120B array processor. The goal is a power flow which will solve a 1000-bus problem in less than 0.5 second from a "flat start". The parallelism afforded by the functional units of the AP- 120B have a pronounced effect on how the algorithm is implemented. The sparse linear equation solver dictates the hardware options with which the AP-120B should be equipped.