Pseudorandom Stimuli Generation for Testing Time-to-Digital Converters on an FPGA

This paper presents a pulse generator circuit that produces a stream of pulses at pseudorandom time intervals. The proposed circuit may serve as a stimulus generator for code density testing of time-to-digital converters (TDCs). The functional behavior of the circuit was first investigated with a software model coded in C ++. The software simulation showed that the interpulse intervals only uniformly cover their domain at a given resolution if the greatest common divisor between the intervals and the observation window is 1 with respect to a common reference clock. In a second step, the circuit was implemented in hardware using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) and tested on a Xilinx Spartan-3 field-programmable gate array (FPGA) platform. The pulse density histograms obtained from the software and hardware test cases show pulse distributions with nonlinearity values within one least significant bit (LSB). In the end, the circuit was used as a stimulus generator for code density testing of a TDC circuit on an FPGA.