DocumentCode :
1165860
Title :
Logic synthesis for field-programmable gate arrays
Author :
Hwang, Ting-Ting ; Owens, Robert Michael ; Irwin, Mary Jane ; Wang, Kuo Hua
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Volume :
13
Issue :
10
fYear :
1994
fDate :
10/1/1994 12:00:00 AM
Firstpage :
1280
Lastpage :
1287
Abstract :
In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA´s) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices
Keywords :
circuit layout CAD; communication complexity; logic CAD; logic arrays; many-valued logics; optimisation; CAD; FPGA synthesis; communication complexity-based decomposition technique; field-programmable gate arrays; logic embedding; logic optimization; logic synthesis technique; multilevel logic synthesis; technology mapping; Circuit synthesis; Complexity theory; Computer science; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic devices; Programmable logic arrays; Table lookup; Very large scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.317471
Filename :
317471
Link To Document :
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