On yield consideration for the design of redundant programmable logic arrays

Redundancy techniques have been applied to conventional programmable logic arrays (PLAs) to allow for the repair of defective chips. When the redundancy technique is implemented in a VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area, and the additional spare lines can increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair defective chip; then the additional spare lines may increase rather than decrease the chip yields. The possibility of yield enhancement through redundant design is analyzed, showing that the chip yield is increased significantly