DocumentCode :
1170818
Title :
Parallel decoding cyclic burst error correcting codes
Author :
Umanesan, Ganesan ; Fujiwara, Eiji
Author_Institution :
Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan
Volume :
54
Issue :
1
fYear :
2005
fDate :
1/1/2005 12:00:00 AM
Firstpage :
87
Lastpage :
92
Abstract :
Burst error correcting codes, such as fire codes, have traditionally been decoded using linear feedback shift registers (LFSR). However, such sequential decoding schemes are not suitable for modern ultra high-speed channels that demand high-speed parallel decoding employing only combinational logic circuitry. This work proposes a parallel decoding method for cyclic burst error correcting codes. Under this method, a binary companion matrix T defines the entire decoding process. Hence, the decoding method can be implemented using only combinational logic.
Keywords :
combinational circuits; cyclic codes; decoding; error correction codes; matrix multiplication; shift registers; binary companion matrix; combinational logic circuitry; cyclic burst error correcting codes; fire codes; linear feedback shift registers; parallel decoding; Combinational circuits; Decoding; Error correction codes; Fires; Hardware; Holographic optical components; Linear feedback shift registers; Logic; Parity check codes; Polynomials; 65; Fire codes; Index Terms- Cyclic burst error correcting codes; companion matrix.; parallel decoding;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/TC.2005.9
Filename :
1362643
Link To Document :
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