Wiring control by RTL design for reconfigurable wave-pipelined circuits

High-speed and low-power circuits of considering the development cycle for digital signal processing are very important in a mobile computing. The achievement of them on an FPGA (Field Programmable Gate Array) dominant in the point of shortening the development cycle. Nevertheless a reconfigurable device such as an FPGA for a power-aware design has not been developed. The authors have developed logic blocks for reconfigurable wave-pipelined circuits for the achievement of high-speed and low-power reconfigurable circuits. Wave-pipeline is one of a circuit design technique for high-speed processing and low-power consumption. They are very useful for the reduction in the resource on the FPGA. However, a wiring control to connect them have not been achieved. In this paper, the wiring control by RTL Design is developed. Its operation speeds are evaluated using 0.18 um CMOS technology.