Effect of annealing after copper plating on the pumping behavior of through silicon vias

Though Silicon Vias(TSVs) are regarded as a key technology to achieve three dimensional(3D) integrated circuit(IC) functionality. Annealing a silicon device with TSVs may cause high stress and cause TSV protrusion because of high Coefficient of Thermal Expansion(CTE) between silicon substrate and TSVs. The TSV wafers could be annealed right after copper plating process, or after chemical mechanical polish (CMP) process, or both. In this paper, we report our research progress on the effect of annealing right after copper plating on the pumping behavior at different temperatures. Then the copper overburden is removed by CMP. The TSV wafers are tested at different temperatures for 30 minutes, 250°C, 300°C, 350°C, 400°C, 450°C, respectively. The pumping is measured by optical profiler, BRUKER Contour GT-X3. The finite element analysis method, ANSYS, is used to model and simulate the copper pumping at different temperatures. The pumping results with annealing at different temperatures are compared with those without annealing. It reveals that the pumping with annealing is larger than that without annealing. This is possibly due to higher level of stress release and microstructure evolution.