Test chip based approach to automated diagnosis of CMOS yield problems

The authors describe a design approach for, and experimental results obtained from, a test chip developed for the purpose of automated diagnosis of random-defect-dominated yield problems of CMOS ICs. Unlike test chips comprised of ad hoc collections of test structures, the test chip described here is based on the notion of systematic structural decomposition, employed to ensure complete sets of structures required for unambiguous identification of all structural features associated with electrical faults. Test structure selection, sizing, layout, testing, and data analysis are discussed, and examples of rejected wafers are presented to illustrate the direct and straightforward way in which unambiguous diagnosis are obtained. Conclusions related to implementation of an expert system for automated CMOS process problem diagnosis employing the data obtained from this test chip are summarized