Title :
Stress control of plasma enhanced chemical vapor deposited SiO2 film in through silicon via process
Author :
Wenguo Ning ; Qiang Zhao ; Kai Zheng ; Dong Chen ; Hongyan Guo ; Li Zhang ; Zhengxun Hu ; Tan, K.H. ; Lai, C.M.
Author_Institution :
Jiangyin Changdian Adv. Packaging Co., Ltd., Jiangyin, China
Abstract :
Through silicon via is an essential element for three dimension integration. Excessive stress have potential effects on the reliability of the structure. One concern is the peeling problem of SiO2 layer. It was found that it is caused by the electroplated copper during later solder reflow process. We also found that it is possible to ameliorate the peeling problem by increasing the compressive stress in the SiO2. We found that the peeling problem is solved when SiO2 was deposited with higher compressive stress. Compared to 90% peeling off for compressive stress -20 MPa in the SiO2, Only 20% peeling off for compressive stress -40 MPa in the SiO2 and no peeling off for compressive stress -110 MPa and -150 MPa in the SiO2.
Keywords :
electroplating; integrated circuit reliability; plasma CVD; silicon; silicon compounds; stress control; three-dimensional integrated circuits; compressive stress; electroplated copper; peeling problem; plasma-enhanced chemical vapor deposited silicon dioxide film; silicon dioxide layer; solder reflow process; stress control; structure reliability; three-dimension integration; through silicon via process; Compressive stress; Copper; Reliability; Silicon; Substrates; Through-silicon vias; SiO2; Stress; TSV; peeling;
Conference_Titel :
Electronic Packaging Technology (ICEPT), 2014 15th International Conference on
Conference_Location :
Chengdu
DOI :
10.1109/ICEPT.2014.6922662