Title :
10 GHz full-rate clock and data recovery circuit in 0.18 μm CMOS without external reference clock
Author :
Gu, Z. ; Thiede, A.
Author_Institution :
Univ. of Paderborn, Germany
Abstract :
The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 μm digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mVpp pseudorandom bit Sequence input data of length 231-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.
Keywords :
CMOS digital integrated circuits; MMIC; digital phase locked loops; integrated circuit design; integrated circuit noise; jitter; phase noise; random sequences; synchronisation; 0.18 micron; 1 MHz; 1.1 ps; 1.8 V; 10 GHz; 200 MHz; 205 mA; 250 mV; 7.9 ps; clock phase noise; clock signal recovery; data recovery circuit; digital CMOS technology; full-rate clock circuit; injection phase locked loop technique; monolithic integrated circuit design; pseudorandom bit sequence; root mean square jitter;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20046728
