Investigation of warpage induced reliability of a system in package in assembly process

Author

Qiuxiao Qian ; Yong Liu

Author_Institution

Package Dev., Fairchild Semicond. (Suzhou) Co., Ltd., Suzhou, China

fYear

2014

fDate

12-15 Aug. 2014

Firstpage

718

Lastpage

723

Abstract

The power system in package (SIP) includes multiple chips such as power IGBT, diodes and IC controllers. With more chips encapsulated in one single package, the silicon die crack failure is becoming more and more challenging. In this paper, a leadframe based power SIP package is investigated. The warpage induced reliability in assembly process is studied. The initial leadframe pad warpage will induce high tensile stress in silicon die during clamping process. A 3D FEA model for the assembly clamping process is developed. Parametric modeling DoE is carried out to simulate the impact of different leadframe warpage shape (concave and convex), different lead frame pad warpages, different die sizes, different leadframe thickness and different BLTs.

Keywords

assembling; clamps; design of experiments; encapsulation; finite element analysis; reliability; stress analysis; system-in-package; 3D FEA model; BLTs; DoE parametric modeling; IC controllers; assembly clamping process; assembly process; chip encapsulation; diodes; high tensile stress; lead frame pad warpages; leadframe based power SIP package; leadframe thickness; leadframe warpage shape; multiple chips; one single package; power IGBT; silicon die crack failure; system in package; warpage induced reliability; Ceramics; Clamps; Finite element analysis; Insulated gate bipolar transistors; Lead; Silicon; Tensile stress; FEA; System in package (SIP); aseembly; clamping; lead frame; warpage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Packaging Technology (ICEPT), 2014 15th International Conference on

Conference_Location

Chengdu

Type

conf

DOI

10.1109/ICEPT.2014.6922752

Filename

6922752