DocumentCode :
1185932
Title :
Modeling of power supply noise in large chips using the circuit-based finite-difference time-domain method
Author :
Choi, Jinseong ; Swaminathan, Madhavan ; Do, Nhon ; Master, Raj
Author_Institution :
Adv. Micro Devices Inc., Sunnyvale, CA, USA
Volume :
47
Issue :
3
fYear :
2005
Firstpage :
424
Lastpage :
439
Abstract :
In this paper, a multilayered on-chip power distribution network consisting of two million passive elements has been modeled using the finite-difference time-domain (FDTD) method. In this method, a branch capacitor has been used. The use of the branch capacitor is important for simulating multilayered power grids. In addition, a method for including the CMOS inverter characteristics into the FDTD simulation has been presented. As an example of the application of this method, an H-tree clock network was simulated to compute the power supply noise distribution across an entire chip. Various scenarios with varying decoupling capacitances, load capacitances, number of clock buffers, and rise times have been analyzed to demonstrate the importance of circuit nonlinearity on power supply noise. Also, a method has been presented for analyzing package and board planes. Based on the methods presented, the interaction between chip and package has been discussed for capturing the resonant behavior that is otherwise absent when each section of the system is analyzed separately.
Keywords :
CMOS analogue integrated circuits; finite difference time-domain analysis; integrated circuit noise; invertors; power supply circuits; CMOS inverter; FDTD method; H-tree clock network; branch capacitor; circuit nonlinearity; circuit-based finite difference time-domain method; clock buffers; decoupling capacitances; large chips; load capacitances; multilayered onchip power distribution network; passive element; power supply noise distribution; rise times; Capacitance; Capacitors; Circuit noise; Circuit simulation; Clocks; Computational modeling; Finite difference methods; Packaging; Power supplies; Time domain analysis; Chip-package interaction; circuit finite-difference time-domain (FDTD); decoupling capacitor; large chips; on-chip power distribution; power supply noise; wafer level package;
fLanguage :
English
Journal_Title :
Electromagnetic Compatibility, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9375
Type :
jour
DOI :
10.1109/TEMC.2005.851719
Filename :
1516213
Link To Document :
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