Title :
A 32-bank 256-Mb DRAM with cache and TAG
Author :
Tanoi, Satoru ; Tanaka, Yasuhiro ; Tanabe, Tetsuy ; Kita, Akio ; Inada, Toshio ; Hamazaki, Ryoji ; Ohtsuki, Yoshio ; Uesugi, Masaru
Author_Institution :
Electron. Devices Group, OKI Electr. Ind. Co. Ltd., Tokyo, Japan
fDate :
11/1/1994 12:00:00 AM
Abstract :
A 125 megabyte/s synchronous 32-bank 256-Mb DRAM has been developed by a bank-interleaving oriented multibank architecture including a shared-sense amplifier cache with an overlapped bank control for hidden precharge, phase-aligned timing pulse transmission, and voltage controlled negative conductance (VCNC) data-bus current sense amplifier
Keywords :
CMOS integrated circuits; DRAM chips; amplifiers; electric admittance; shared memory systems; synchronisation; 125 Mbyte/s; CMOS integrated memory circuits; DRAM; TAG; bank-interleaving oriented multibank architecture; data-bus current sense amplifier; hidden precharge; overlapped bank control; phase-aligned timing pulse transmission; shared-sense amplifier cache; synchronous; voltage controlled negative conductance; Batteries; Circuits; Pulse amplifiers; Random access memory; Size control; Space technology; Technical Activities Guide -TAG; Time of arrival estimation; Timing; Voltage control;
Journal_Title :
Solid-State Circuits, IEEE Journal of
