Abstract :
A tutorial on the reduced instruction set computer (RISC) approach is presented and the key design issues involved in RISC architecture are highlighted. The results of a number of studies on the instruction execution characteristics of compiled high-level-language programs are examined first. The results of these studies inspired the RISC movement. Approaches to tree key RISC design issues are then summarized: optimized register usage, reduced instruction sets, and pipelining. As examples, an experimental system, the Berkeley RISC and a commercial system, the MIPS R2000, are presented. The advantages and disadvantages of a RISC versus CISC (complex instruction set computer) architecture are also discussed
Keywords :
pipeline processing; reduced instruction set computing; Berkeley RISC; CISC; MIPS R2000; RISC architecture; compiled high-level-language programs; complex instruction set computer; instruction execution characteristics; optimized register usage; pipelining; reduced instruction set computer; Computer aided instruction; Computer architecture; Costs; Design optimization; Hardware; Instruction sets; Pipeline processing; Programming profession; Reduced instruction set computing; Registers;
