• DocumentCode
    1189439
  • Title

    Introduction to high-level synthesis

  • Author

    Gajski, Daniel D. ; Ramachandran, Loganath

  • Author_Institution
    California Univ., Irvine, CA, USA
  • Volume
    11
  • Issue
    4
  • fYear
    1994
  • Firstpage
    44
  • Lastpage
    54
  • Abstract
    The basic problem of high-level synthesis is the mapping of a behavioral description of a digital system into an RTL design consisting of a data path and a control unit. The authors introduce the FSMD model, which forms the basis for synthesis. They discuss the main considerations in a high-level synthesis environment: the input description language, the internal representation, and the main synthesis tasks-allocation, scheduling, and binding. They conclude with some problems that must be solved to make high-level synthesis a widely accepted methodology.<>
  • Keywords
    high level synthesis; logic design; scheduling; FSMD model; RTL design; allocation; behavioral description; binding; high-level synthesis; high-level synthesis environment; input description language; internal representation; scheduling; synthesis tasks; Control system synthesis; Design automation; Design methodology; High level synthesis; Integrated circuit synthesis; Logic circuits; Logic design; Process design; Productivity; Technology management;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.329454
  • Filename
    329454