Title :
RH: a versatile family of reduced hypercube interconnection networks
Author :
Ziavras, Sotirios G.
Author_Institution :
Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA
fDate :
11/1/1994 12:00:00 AM
Abstract :
The binary hypercube has been one of the most frequently chosen interconnection networks for parallel computers because it provides low diameter and is so robust that it can very efficiently emulate a wide variety of other frequently used networks. However, the major drawback of the hypercube is the increase in the number of communication channels for each processor with an increase in the total number of processors in the system. This drawback has a direct effect on the very large scale integration complexity of the hypercube network. This short note proposes a new topology that is produced from the hypercube by a uniform reduction in the number of edges for each node. This edge reduction technique produces networks with lower complexity than hypercubes while maintaining, to a high extent, the powerful hypercube properties. An extensive comparison of the proposed reduced hypercube (RH) topology with the conventional hypercube is included. It is also shown that several copies of the popular cube-connected cycles network can be emulated simultaneously by an RH with dilation 1
Keywords :
VLSI; computational complexity; hypercube networks; parallel architectures; RH; binary hypercube; communication channels; edge reduction technique; low diameter; lower complexity; parallel computers; popular cube-connected cycles network; reduced hypercube interconnection networks; reduced hypercube topology; topology; very large scale integration complexity; Circuit faults; Circuit testing; Computer networks; Concurrent computing; Doped fiber amplifiers; Hypercubes; Integrated circuit interconnections; Multiprocessor interconnection networks; Network topology; Sufficient conditions;
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on