Designing interconnection buses in VLSI and WSI for maximum yield and minimum delay

Exact expressions for the yield of an interconnection bus as a function of its physical dimensions and the parameters and distribution of the possible open-circuit and short-circuit defects are derived. The effect of introducing redundancy into the bus is examined and the optimal layout of a given bus (with and without redundancy) is obtained. Any change in the layout of a bus may affect the propagation delay of the bus and, as a consequence, the performance of the VLSI chip. Hence, the delay of the designed bus in addition to its yield must be taken into account when determining the final layout of the bus. Both yield and delay are discussed through several numerical examples.<>