DocumentCode
1192196
Title
Output-queued switch emulation by fabrics with limited memory
Author
Magill, Robert B. ; Rohrs, Charles E. ; Stevenson, Robert L.
Author_Institution
Dept. of Electr. Eng., Univ. of Notre Dame, IN, USA
Volume
21
Issue
4
fYear
2003
fDate
5/1/2003 12:00:00 AM
Firstpage
606
Lastpage
615
Abstract
The output-queued (OQ) switch is often considered an ideal packet switching architecture for providing quality-of-service guarantees. Unfortunately, the high-speed memory requirements of the OQ switch prevent its use for large-scale devices. A previous result indicates that a crossbar switch fabric combined with lower speed input and output memory and two times speedup can exactly emulate an OQ switch; however, the complexity of the proposed centralized scheduling algorithms prevents scalability. This paper examines switch fabrics with limited memory and their ability to exactly emulate an OQ switch. The switch architecture of interest contains input queueing, fabric queueing, flow-control between the limited fabric buffers and the inputs, and output queueing. We present sufficient conditions that enable this combined input/fabric/output-queued switch with two times speedup to emulate a broad class of scheduling algorithms operating an OQ switch. Novel scheduling algorithms are then presented for the scalable buffered crossbar fabric. It is demonstrated that the addition of a small amount of memory at the crosspoints allows for distributed scheduling and significantly reduces scheduling complexity when compared with the memoryless crossbar fabric. We argue that a buffered crossbar system performing OQ switch emulation is feasible for OQ switch schedulers such as first-in-first-out, strict priority and earliest deadline first, and provides an attractive alternative to both crossbar switch fabrics and to the OQ switch architecture.
Keywords
buffer storage; computational complexity; packet switching; quality of service; queueing theory; telecommunication congestion control; OQ switch architecture; QoS guarantees; centralized scheduling algorithm complexity; crossbar switch fabric; crossbar switch fabrics; distributed scheduling; earliest deadline first scheduler; fabric buffers; fabric queueing; first-in-first-out scheduler; flow-control; high-speed memory requirements; input memory; input queueing; input/fabric/output-queued switch; large-scale devices; limited memory fabrics; memoryless crossbar fabric; output memory; output queueing; output-queued switch emulation; packet switching architecture; quality-of-service guarantees; scalable buffered crossbar fabric; scheduling complexity reduction; strict priority scheduler; sufficient conditions; Emulation; Fabrics; Large-scale systems; Packet switching; Quality of service; Read-write memory; Scalability; Scheduling algorithm; Switches; Throughput;
fLanguage
English
Journal_Title
Selected Areas in Communications, IEEE Journal on
Publisher
ieee
ISSN
0733-8716
Type
jour
DOI
10.1109/JSAC.2003.810532
Filename
1197705
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