Title :
A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability
Author :
Hamamoto, Takeshi ; Minami, Yoshihiro ; Shino, Tomoaki ; Kusunoki, Naoki ; Nakajima, Hiroomi ; Morikado, Mutsuo ; Yamada, Takashi ; Inoh, Kazumi ; Sakamoto, Atsushi ; Higashi, Tomoki ; Fujita, Katsuyuki ; Hatsuda, Kosuke ; Ohsawa, Takashi ; Nitayama, Akih
Author_Institution :
Center for Semicond. Res. & Dev., Toshiba Corp., Yokohama
fDate :
3/1/2007 12:00:00 AM
Abstract :
A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage
Keywords :
CMOS integrated circuits; DRAM chips; copper; silicon-on-insulator; 128 MByte; 45 nm; 90 nm; CMOS technology; Cu; DRAM chips; bit line; device simulation; dynamic random access memory; electric field; floating-body cell; silicon-on-insulator; source line; CMOS process; CMOS technology; Circuits; DRAM chips; Design optimization; Random access memory; Scalability; Signal processing; Silicon on insulator technology; Wiring; DRAM chips; MOSFETs; hot carriers; silicon-on-insulator (SOI) technology;
Journal_Title :
Electron Devices, IEEE Transactions on
DOI :
10.1109/TED.2006.890597
