DocumentCode
1194232
Title
Compact model development for a new nonvolatile memory cell architecture
Author
O´Shea, Mike ; Duane, Russell ; McCarthy, Diarmuid ; McCarthy, Kevin G. ; Concannon, Ann ; Mathewson, Alan
Author_Institution
Nat. Microelectron. Res. Centre, Cork, Ireland
Volume
16
Issue
2
fYear
2003
fDate
5/1/2003 12:00:00 AM
Firstpage
215
Lastpage
219
Abstract
To facilitate the development of system-on-chip designs, accurate models are required for each of the new elements being included. In this paper, a new model for a novel low power flash memory device, the top floating gate cell, which can be integrated into CMOS processes with minimal disruption to the standard process is described.
Keywords
CMOS memory circuits; SPICE; flash memories; integrated circuit modelling; low-power electronics; system-on-chip; CMOS process integration; SPICE compatible model; compact model development; drain current drain voltage characteristics; low power flash memory device; nonvolatile memory cell architecture; system-on-chip designs; top floating gate cell; CMOS process; CMOS technology; Flash memory; Memory architecture; Nonvolatile memory; Power system modeling; Semiconductor device modeling; Silicon; System-on-a-chip; Tunneling;
fLanguage
English
Journal_Title
Semiconductor Manufacturing, IEEE Transactions on
Publisher
ieee
ISSN
0894-6507
Type
jour
DOI
10.1109/TSM.2003.811576
Filename
1198031
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