Title :
Nanoscale FD/SOI CMOS: thick or thin BOX?
Author :
Trivedi, V.P. ; Fossum, J.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA
Abstract :
The question of buried-oxide (BOX) thickness scaling for nanoscale fully depleted (FD) silicon-on-insulator (SOI) CMOS is addressed via insightful quantitative and qualitative analyses. Whereas, FD/SOI MOSFETs with thin BOX give better control of short-channel effects (SCEs), they complicate the material and/or process technologies and undermine CMOS speed. We show that the improved SCE control afforded by thin BOX is due to high transverse electric field in the body defined by the device asymmetry, and not only to the suppression of electric-field fringing in the BOX as is commonly presumed. Since conventional FD/SOI CMOS with thick BOX can be scaled via ultrathin bodies, we conclude that thin BOX is not needed nor desirable.
Keywords :
CMOS integrated circuits; MOSFET; electric fields; nanotechnology; silicon-on-insulator; FD-SOI MOSFET; Si; buried-oxide thickness scaling; electric-field fringing; nanoscale fully depleted; short-channel effects control; silicon-on-insulator CMOS; thin BOX; transverse electric field; ultrathin-body MOSFET; CMOS process; CMOS technology; Circuit simulation; FinFETs; MOSFETs; Nanoscale devices; Numerical simulation; Silicon on insulator technology; Transconductance; Wafer bonding; Buried-oxide (BOX) thickness; fully depleted (FD) silicon-on-insulator (SOI) CMOS; ultrathin-body (UTB) MOSFET;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2004.839624