• DocumentCode
    1194367
  • Title

    Process sensitivity and robustness analysis of via-first dual-damascene process

  • Author

    Tsui, Bing-Yue ; Chen, Chih-Wei ; Huang, Shien-Ming ; Lin, Shyue-Shyh

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    16
  • Issue
    2
  • fYear
    2003
  • fDate
    5/1/2003 12:00:00 AM
  • Firstpage
    307
  • Lastpage
    313
  • Abstract
    Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as the via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process development is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between the inter-metal-dielectric and SACL material are preferred. The SACL thickness in the via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16 μm. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-μm technology node.
  • Keywords
    copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit yield; protective coatings; semiconductor process modelling; sensitivity analysis; sputter etching; 0.13 micron; 0.13-μm technology node; 0.27 to 0.16 micron; Cu; SACL breakthrough step; SACL process development; capping layer thickness; four-step procedure; inter-metal dielectric; medium etch rate selectivity; overetching percentage; process sensitivity; process window; robustness analysis; sacrificial layer coating; sealing layer protection; shallow trench depth; trench etching; underlying copper lines; via chain yield; via density; via size; via-first dual-damascene process; Coatings; Copper; Councils; Etching; Industrial electronics; Plasma applications; Protection; Robustness; Scalability; Wiring;
  • fLanguage
    English
  • Journal_Title
    Semiconductor Manufacturing, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0894-6507
  • Type

    jour

  • DOI
    10.1109/TSM.2003.811887
  • Filename
    1198044