DocumentCode :
1195462
Title :
Data Bus Inversion in High-Speed Memory Applications
Author :
Hollis, Timothy M.
Author_Institution :
Micron Technol., Inc., Boise, ID
Volume :
56
Issue :
4
fYear :
2009
fDate :
4/1/2009 12:00:00 AM
Firstpage :
300
Lastpage :
304
Abstract :
Efforts to reduce high-speed memory interface power have led to the adoption of data bus inversion or bus-invert coding. This study compares two popular algorithms, which seek to limit the number of simultaneously transitioning signals and bias the state of transmitted data toward a preferred binary level, respectively. A new algorithm, which provides a compromise between transition frequency and preferred signal level, is proposed, and the three algorithms are compared in terms of their impact on power consumption, power supply noise reduction, and general signal integrity enhancement when used in conjunction with a variety of link topologies.
Keywords :
field buses; storage management chips; binary level; bus-invert coding; data bus inversion; high-speed memory; power consumption; power supply noise reduction; signal integrity enhancement; transition frequency; Bus-invert coding; data bus inversion (DBI); single-ended signaling; transmission line termination;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2009.2015395
Filename :
4801969
Link To Document :
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