Abstract :
A new modeling approach for simulation and verification of digital designs is presented in this paper and has been implemented for functional and fault simulation and timing verification in the experimental rule-based design verifier (RDV) [5] at. Stanford University that uses Ada [2], [6] as the hardware description language and a simulation environment. In this approach, every component of a digital design is represented as a model-a concurrently executable entity that performs the tasks of scheduling itself for execution, simulation, or verification of the corresponding component, and communication of results to other devices. A model schedules itself for execution when the necessary signals are asserted at all its input ports. New approaches are developed and presented in this paper that permit the functional fault simulation and timing verification tasks to be distributed in all the models. Corresponding to an output signal generated as a result of execution of a component description, the model retrieves a list of components that are connected to its output port and propagates the signal directly to each of them. As a consequence of the distributed scheduling and communication mechanisms, parallelism may be utilized with relative ease.
