DocumentCode :
1197340
Title :
A test methodology for wafer scale system
Author :
Landis, David L.
Author_Institution :
Center for Microelectron. Res., Univ. of South Florida, Tampa, FL, USA
Volume :
11
Issue :
1
fYear :
1992
fDate :
1/1/1992 12:00:00 AM
Firstpage :
76
Lastpage :
82
Abstract :
To efficiently access and control on-chip design for test (DFT) circuitry, a standard test interface is required. A uniform testing interface is defined for each functional cell, with built-in self-test incorporated whenever possible. Use of a standard interface will reduce test complexity and costs by allowing entire wafer probing by a common standardized probe card, irrespective of the number of different functional cell types. Details are provided for the function, cell, and wafer level testing standards as well as for the procedures to be followed at wafer level restructuring and test. The test overhead area required is assessed; and for a large class of designs, the benefit of reduced input/output (I/O) area is found to more than compensate for the added test area
Keywords :
VLSI; automatic testing; built-in self test; digital integrated circuits; integrated circuit testing; WSI; built-in self-test; standard test interface; standardized probe card; test methodology; test overhead area; wafer probing; wafer scale system; Automatic testing; Built-in self-test; Circuit testing; Costs; Design for testability; Integrated circuit interconnections; Microelectronics; Probes; System testing; Wafer scale integration;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.108620
Filename :
108620
Link To Document :
بازگشت