Title :
DFE architectures for high-speed backplane applications
Author :
Li, M. ; Wang, S. ; Kwasniewski, T.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 μm CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane.
Keywords :
CMOS integrated circuits; decision feedback equalisers; 0.18 micron; 10 Gbit/s; CMOS technology; DFE architectures; FR4 backplane; embedded decision feedback equalisation; high-speed backplane application; look-ahead decision feedback equalisation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20052206
