Title :
A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications
Author :
Morishita, Fukashi ; Hayashi, Isamu ; Matsuoka, Hideto ; Takahashi, Kazuhiro ; Shigeta, Kuniyasu ; Gyohten, Takayuki ; Niiro, Mitsutaka ; Noda, Hideyuki ; Okamoto, Mako ; Hachisuka, Atsushi ; Amo, Atsushi ; Shinkawata, Hiroki ; Kasaoka, Tatsuo ; Dosaka, K
Author_Institution :
Renesas Technol. Corp., Hyogo, Japan
Abstract :
An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm2 16-Mb embedded DRAM macro is fabricated in 0.13 μm logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-μW data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.
Keywords :
CMOS memory circuits; DRAM chips; MIM devices; embedded systems; integrated circuit design; mobile handsets; system-on-chip; 0.13 micron; 1.2 V; 16 Mbit; 312 MHz; 73 muW; CMOS memory integrated circuits; MIM capacitors; array control signals; co-salicide word lines; high-speed array operation; mobile applications; negative edge transmission; power-down data retention mode; random-cycle embedded DRAM macro; self-adjustable timing control; system-on-chip; Application specific integrated circuits; Circuit testing; Delay; MIM capacitors; Personal digital assistants; Random access memory; System-on-a-chip; Temperature control; Timing; Voltage control; CMOS memory integrated circuits; embedded DRAM; mobile applications; system-on-chip;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2004.837986
