Current mode, low-power, on-chip signaling in deep-submicron CMOS technology

This paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10%. Experimental results on a set of benchmark signaling problems implemented in a 0.25-μm 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a two-fold reduction in the power and a reduction of 1.4 times the area.