A discrete state-space model for SSR stabilizing controller design for TCSC compensated systems

A sampled-data model for a thyristor controlled series capacitor compensated system is derived for use in stabilizing controller design for subsynchronous modes of oscillation. The model is a refinement of the existing models based on the Poincare/spl acute/ mapping techniques already developed in the literature. The special features of the model are to increase the sampling frequency to six times the synchronous frequency and to directly express the small signal variation of the state of the whole system on the variation of the thyristor firing angles. The effectiveness of the model is shown by using it to design an all stabilizing controller for the IEEE First SSR Benchmark Model.