DocumentCode

1200978

Title

Correction to "Reducing computing time in the analysis of networks by digital computer"

Author

Mayeda, W.

Volume

6

Issue

4

fYear

1959

fDate

12/1/1959 12:00:00 AM

Firstpage

394

Lastpage

394

Keywords

Circuit theory; Computer networks; Delay effects; Joining processes; Signal generators; Tree graphs;

fLanguage

English

Journal_Title

Circuit Theory, IRE Transactions on

Publisher

ieee

ISSN

0096-2007

Type

jour

DOI

10.1109/TCT.1959.1086585

Filename

1086585