Title :
Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In
Author :
Bahukudumbi, Sudarshan ; Chakrabarty, Krishnendu
Author_Institution :
Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC, USA
Abstract :
Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern ordering technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is formulated and solved optimally using integer linear programming. Efficient heuristic methods are also presented to easily solve the pattern-ordering problem for large circuits. Simulation results are presented for the ISCAS´89 and the IWLS´05 benchmark circuits, and the proposed ordering technique is compared with two baseline methods that carry out pattern ordering to minimize peak power and average power, respectively. A third baseline method that randomly orders test patterns is also used to evaluate the proposed methods.
Keywords :
benchmark testing; heuristic programming; power consumption; semiconductor device manufacture; semiconductor device testing; ISCAS´89; IWLS´05; baseline method; benchmark circuits; die power variations; efficient heuristic methods; integer linear programming; large circuits; power consumption variation; power management; scan-based testing; semiconductor manufacturing; test-pattern application; test-pattern ordering; wafer-level test-during-burn-in technique; Wafer-level test during burn-in (WLTBI); test power; test-pattern ordering;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2008.2006679