Title :
Epoxy encapsulation on ceramic quad flat packs (CQFPs)
Author :
Clementi, J. ; Carden, T. ; Engle, S.
Author_Institution :
Microelectron. Div., IBM Corp., Endicott, NY, USA
fDate :
12/1/1994 12:00:00 AM
Abstract :
The ceramic quad fat pack (CQFP) is a high-performance, low-cost technology for surface mount applications. It is an extension of the metallized ceramic (MC) and metallized ceramic with polyimide (MCP) product base. These finished modules conform to JEDEC I/O and footprint standards. The packages are available in 0.5 mm and 0.4 mm lead pitches with flexibility to address unique application requirements such as body sizes or lead counts/pitches. Semiconductor die interconnection is performed using either flip chip (controlled collapse chip connection-C4) attach or wirebonding. Excellent package reliability with no intrinsic wear-out failure mechanism results by encapsulating solder joints from the silicon C4 die and peripheral lead to ceramic carrier. IBM evaluated several encapsulant configurations, and tested over 2000 encapsulated carriers and 897000 individual solder joints during development and qualification. Reliability data was collected for a variety of stress tests and conditions. Both solder connections show a dramatic order of magnitude fatigue life improvement when encapsulation is used. Encapsulant selection has been made based on mechanical, electrical, and thermal requirements to meet package performance and reliability objectives. The sensitivity of material properties to process variables such as encapsulant dispense, gel, and cure has been characterized. As a result, material processing limits and conditions have been optimized for manufacturing high production volumes
Keywords :
encapsulation; failure analysis; fatigue; flip-chip devices; integrated circuit packaging; integrated circuit reliability; surface mount technology; 0.4 mm; 0.5 mm; CQFPs; IBM; JEDEC I/O standards; body sizes; ceramic quad flat packs; controlled collapse chip connection; encapsulant dispense; epoxy encapsulation; fatigue life improvement; flip chip; footprint standards; high production volumes; lead pitches; material properties; package reliability; reliability data; semiconductor die interconnection; solder joints; stress tests; surface mount applications; wear-out failure; Ceramics; Electronics packaging; Encapsulation; Lead; Metallization; Polyimides; Semiconductor device packaging; Soldering; Surface-mount technology; Testing;
Journal_Title :
Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on